The invention generally relates to providing a low phase noise reference clock signal, such as a reference clock signal for a phase locked loop, for example.
A modern communication system typically includes a tunable frequency synthesizer for purposes of generating mixing signals for the system. The frequency synthesizer typically includes a phase locked loop (PLL) and a reference clock generator that provides a reference clock signal to the PLL. The PLL generates the output signal for the synthesizer; and the frequency of the output signal typically is a multiple of the frequency of the reference clock signal. The frequency ratio typically is established by a programmable feedback divider of the PLL.
Modern wideband communications systems have frequency synthesizers that can be tuned over a very wide range at multi-GHz frequencies. It may be desirable for the PLL to have a relatively large bandwidth for purposes of rejecting phase noise that is generated by the controlled oscillator of the PLL. However, a large loop bandwidth may cause the reference clock signal to significantly contribute to the phase noise (i.e., the clock jitter) in the output signal of the synthesizer. The large ratio between the output clock frequency (in the GHz range, for example) and the reference clock frequency (in a tens of MHz range, for example) typically results in a large feedback divider modulus for the PLL and thus, a large gain for the phase noise and the spurious tones that exist in the reference clock path.
Thus, there exists a continuing need for a frequency synthesizer that has a reference clock signal path that introduces an insignificant amount of phase noise and spurious tones to the reference clock signal.